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RF3166
0
Typical Applications * 3V Quad-Band GSM Handsets * Commercial and Consumer Systems * Portable Battery-Powered Equipment Product Description
1
RoHS Compliant & Pb-Free Product
QUAD-BAND GSM850/GSM900/DCS/PCS POWER AMP MODULE
* GSM850/EGSM900/DCS/PCS Products * GPRS Class 12 * Power StarTM Module
1.40 1.25
The RF3166 is a high-power, high-efficiency power amplifier module with integrated power control that provides over 50dB of control range. The device is a self-contained 6mmx6mm module with 50 input and output terminals. The device is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. The RF3166 incorporates RFMD's latest VBATT tracking circuit, which monitors battery voltage and prevents the power control loop from reaching saturation. The VBATT tracking circuit eliminates the need to monitor battery voltage, thereby minimizing switching transients. The RF3166 requires no external routing or external components, simplifying layout and reducing board space. Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
6.00 0.10
6.00 0.10 Shaded areas represent pin 1.
0.450 0.075
Dimensions in mm.
0.100 TYP 0.565 TYP 0.965 1.150 TYP 1.225 TYP 1.750 TYP
2.600 TYP 4.650
5.823 5.500 5.400 TYP 5.225 TYP 5.200 TYP 4.625 TYP 4.450 TYP 3.850 TYP 3.675 TYP 3.075 TYP 2.900 TYP 2.300 TYP 2.125 TYP 1.525 TYP 1.350 TYP 0.800 TYP 0.600 TYP 0.500 TYP 0.000
1
0.000 TYP 0.565 TYP 1.150 TYP 2.000 TYP 2.850 5.057 5.100
Package Style: Module, 6mm x6mm
Features * Ultra-Small 6mmx6mm Package Size * Integrated VREG * Complete Power Control Solution * Automatic VBATT Tracking Circuit * No External Components or Routing * Improved Power Flatness
Ordering Information
DCS/PCS 1 RFIN BAND SELECT 2 TX ENABLE 3 VBATT 4 GND 5 VRAMP 6 GSM 7 RF IN
9
DCS/PCS RFOUT
8
GSM RFOUT
Functional Block Diagram
Quad-Band GSM850/GSM900/DCS/PCS Power Amp Module RF3166 SB Power Amp Module 5-Piece Sample Pack RF3166PCBA-410 Fully Assembled Evaluation Board RF3166ASMPCBA-410 Fully Assembled Evaluation Board with Antenna Switch Module RF Micro Devices, Inc. Tel (336) 664 1233 7628 Thorndike Road Fax (336) 664 0454 Greensboro, NC 27409, USA http://www.rfmd.com
RF3166
Rev A3 061031
5.435 TYP 5.500 TYP 5.900 TYP
5.900 TYP 5.435 5.370 5.035 4.600 4.300 4.200 3.800 3.400 3.065 3.000 2.600 2.100 1.700 1.365 1.300 0.900 TYP 0.750 TYP 0.565 TYP 0.100 TYP
2-491
RF3166
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Input RF Power Max Duty Cycle Output Load VSWR Operating Case Temperature Storage Temperature
Rating
-0.3 to +6.0 -0.3 to +2.2 +10 50 10:1 -20 to +85 -55 to +150
Unit
VDC V dBm % C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall Power Control VRAMP
Power Control "ON" Power Control "OFF" VRAMP Input Capacitance VRAMP Input Current TX Enable "ON" TX Enable "OFF" GSM Band Enable DCS/PCS Band Enable
Specification Min. Typ. Max.
Unit
Condition
2.1 0.26 2 1.5 0.5 0.5 1.5 3.5 3.0 4.5 4.5 5.5 1 150 20 30
V V pF A V V V V V V V A mA V V A V V A
Max. POUT, Voltage supplied to the input Min. POUT, Voltage supplied to the input DC to 2MHz VRAMP =2.1V
Overall Power Supply
Power Supply Voltage Specifications Nominal operating limits VRAMP <1.7V PIN <-30dBm, TX Enable=Low, Temp=-20C to +85C VRAMP =0.26V, TX Enable=High
Power Supply Current
Overall Control Signals
Band Select "Low" Band Select "High" Band Select "High" Current TX Enable "Low" TX Enable "High" TX Enable "High" Current 0 1.5 0 1.5 0 2.0 20 0 2.0 1 0.5 3.0 50 0.5 3.0 2
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RF3166
Parameter Specification Min. Typ. Max. Unit Condition
Temp=+25 C, VBATT =3.5V, VRAMP =2.1V, PIN =3dBm, Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s 824 to 849 34.2 32.0 45 0 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <34.2dBm into 50 load Set VRAMP where POUT <34.2dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.26V to 2.1V VRAMP =VRAMP_RP Temp=-20C to +85C, VBATT >3.0V. Ramping shape same as for Condition: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP VBATT =3.0V to 4.5V, Temp=-20C to +85C, PIN =0dBm to 5dBm, Relative to output power for condition: VBATT =3.5V, PIN =+3dBm, Temp=25C, Freq=836.5MHz. Output power variation measured at set VRAMP. Temp=+25C, VBATT =3.5V, VRAMP =2.1V Temp=+85C, VBATT =3.0V, VRAMP =2.1V At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 869MHz to 894MHz, POUT < +34.2dBm TXEnable=Low, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.26V VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to 2.1V
Overall (GSM850 Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Cross Band Isolation at 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
52 +3 -85 -45 -30 -30 -15 -30
+5 -83 -30 -10 -20 -10 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50 50 55 -35 -23
dB dBm dBm
Power Control VRAMP
Power Control Range Transient Spectrum Transient Spectrum Under Extreme Conditions
Power Degradation from Nominal Conditions 5dBm to 14dBm 14dBm to 32dBm
-4 -2
+4 +2
dB dB
Notes: VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
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RF3166
Parameter Specification Min. Typ. Max. Unit Condition
Temp=+25 C, VBATT =3.5V, VRAMP =2.1V, PIN =3dBm, Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s 880 to 915 34.2 32.0 51 0 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <34.2dBm into 50 load Set VRAMP where POUT <34.2dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.26V to 2.1V VRAMP =VRAMP_RP Temp=-20C to +85C, VBATT >3.0V. Ramping shape same as for Condition: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP VBATT =3.0V to 4.5V, Temp=-20C to +85C, PIN =0dBm to 5dBm, Relative to output power for condition: VBATT =3.5V, PIN =+3dBm, Temp=25C, Freq=897.5MHz. Output power variation measured at set VRAMP. Temp=+25C, VBATT =3.5V, VRAMP =2.1V Temp=+85C, VBATT =3.0V, VRAMP =2.1V At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 925MHz to 935MHz, POUT < +34.2dBm RBW=100kHz, 935MHz to 960MHz, POUT < +34.2dBm TXEnable=Low, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.26V VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to 2.1V
Overall (GSM900 Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power
56 +3 -83 -85
+5 -80 -83 -30 -10 -20 -10 -15 -36
Forward Isolation 1 Forward Isolation 2 Cross Band Isolation 2f0 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
-40 -30 -30 -15 -30
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50 50 55 -35 -23
dB dBm dBm
Power Control VRAMP
Power Control Range Transient Spectrum Transient Spectrum Under Extreme Conditions
Power Degradation from Nominal Conditions 5dBm to 14dBm 14dBm to 32dBm
-4 -2
+4 +2
dB dB
Notes: VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
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Parameter Specification Min. Typ. Max. Unit Condition
Temp=25C, VBATT =3.5V, VRAMP =2.1V, PIN =3dBm, Freq=1710MHz to 1785MHz, 25% Duty Cycle, pulse width=1154s 1710 to 1785 32.0 30.0 46 0 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <32dBm into 50 load Set VRAMP where POUT <32dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.26V to 2.1V VRAMP =VRAMP_RP Temp=-20C to +85C, VBATT >3.0V. Ramping shape same as for Condition: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP VBATT =3.0V to 4.5V, Temp=-20C to +85C, PIN =0dBm to 5dBm, Relative to output power for condition: VBATT =3.5V, PIN =+3dBm, Temp=25C, Freq=1747.5MHz. Output power variation measured at set VRAMP. Temp=+25C, VBATT =3.5V, VRAMP =2.1V Temp=+85C, VBATT =3.0V, VRAMP =2.1V At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 1805MHz to 1880MHz, POUT < 32dBm TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.26V, PIN =+5dBm VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to 2.1V
Overall (DCS Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
52 +3 -85 -40 -25 -15 -30
+5 -80 -30 -10 -10 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50 45 50 -35 -23
dB dBm dBm
Power Control VRAMP
Power Control Range Transient Spectrum Transient Spectrum Under Extreme Conditions
Power Degradation from Nominal Conditions 0dBm to 15dBm 15dBm to 30dBm
-4 -2
+4 +2
dB dB
Notes: VRAMP_RP =VRAMP set for 32dBm at nominal conditions.
Rev A3 061031
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RF3166
Parameter Specification Min. Typ. Max. Unit Condition
Temp=25C, VBATT =3.5V, VRAMP =2.1V, PIN =3dBm, Freq=1850MHz to 1910MHz, 25% Duty Cycle, pulse width=1154s 1850 to 1910 32.0 30.0 46 0 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 Spurious<-36dBm, RBW=3MHz Set VRAMP where POUT <32dBm into 50 load Set VRAMP where POUT <32dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad VRAMP =0.26V to 2.1V VRAMP =VRAMP_RP Temp=-20C to +85C, VBATT >3.0V. Ramping shape same as for Condition: Temp=25C, VBATT =3.5V, VRAMP =VRAMP_RP VBATT =3.0V to 4.5V, Temp=-20C to +85C, PIN =0dBm to 5dBm, Relative to output power for condition: VBATT =3.5V, PIN =+3dBm, Temp=25C, Freq=1880MHz. Output power variation measured at set VRAMP. Temp=+25C, VBATT =3.5V, VRAMP =2.1V Temp=+85C, VBATT =3.0V, VRAMP =2.1V At POUT MAX, VBATT =3.5V Maximum output power guaranteed at minimum drive level RBW=100kHz, 1930MHz to 1990MHz, POUT < 32dBm TXEnable=Low, PIN =+5dBm TXEnable=High, VRAMP =0.26V, PIN =+5dBm VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to VRAMP_RP VRAMP =0.26V to 2.1V
Overall (PCS Mode)
Operating Frequency Range Maximum Output Power 1 Maximum Output Power 2 Total Efficiency Input Power Range Output Noise Power Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability
52 +3 -85 -35 -25 -15 -30
+5 -80 -30 -10 -10 -15 -36
50
Output Load VSWR Ruggedness
10:1
Output Load Impedance
50 45 50 -35 -23
dB dBm dBm
Power Control VRAMP
Power Control Range Transient Spectrum Transient Spectrum Under Extreme Conditions
Power Degradation from Nominal Conditions 0dBm to 15dBm 15dBm to 30dBm
-4 -2
+4 +2
dB dB
Notes: VRAMP_RP =VRAMP set for 32dBm at nominal conditions.
2-496
Rev A3 061031
RF3166
Pin 1 2 Function Description Interface Schematic DCS/PCS IN RF input to the DCS band. This is a 50 input. Allows external control to select the GSM or DCS band with a logic high BAND or low. A logic low enables the GSM band whereas a logic high enables BAND SEL SELECT GSM CTRL the DCS band.
TX EN DCS CTRL
3
TX ENABLE
This signal enables the PA module for operation with a logic high.
VBATT
TX EN
TX ON
4 5 6
VBATT GND VRAMP
Power supply for the module. This should be connected to the battery.
Ramping signal from DAC. A 300kHz lowpass filter is integrated into the CMOS. No external filtering is required.
VRAMP
300 kHz
7 8 9 Pkg Base
GSM IN GSM OUT DCS/PCS OUT GND
RF input to the GSM band. This is a 50 input. RF output for the GSM band. This is a 50 output. The output load line matching is contained internal to the package. RF output for the DCS band. This is a 50 output. The output load line matching is contained internal to the package.
Rev A3 061031
2-497
RF3166
Pin Out
Top Down View
DCS/PCS 1 RFIN BAND SELECT 2 TX ENABLE 3 VBATT 4 GND 5 VRAMP 6 GSM 7 RF IN 8 GSM RFOUT 9 DCS/PCS RFOUT
2-498
Rev A3 061031
RF3166
Application Schematic
50 strip DCS/PCS IN BAND SELECT TX ENABLE VBATT 1 2 3 4 5 VRAMP GSM IN 50 strip 6 7 8 50 strip GSM OUT 9 50 strip DCS/PCS OUT
Evaluation Board Schematic
P1 1 GND P2-1 CON1 50 strip DCS/PCS IN 1 BAND SELECT TX ENABLE 2 3 VBATT 22 F* VRAMP 50 strip GSM IN 4 5 6 7 8 50 strip GSM OUT 9 50 strip DCS/PCS OUT P2 1 VCC CON1
Notes: * The value of the VBATT decoupling capacitor depends on the noise level of the phone board. Capacitor type may be either tantalum or ceramic. Some applications may not require this capacitor. 1. All the PA output measurements are referenced to the PA output pad (pins 8 and 9). 2. The 50 strip between the PA output pad and the SMA connector has an approximate insertion loss of 0.1 dB for GSM850/EGSM900 and 0.2 dB for DCS1800/PCS1900 bands.
Rev A3 061031
2-499
RF3166
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-Layer
2-500
Rev A3 061031
RF3166
Theory of Operation
Overview The RF3166 is a quad-band GSM850, EGSM900, DCS1800, and PCS1900 power amplifier module that incorporates an indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop appears as an open loop to the user and can be driven directly from the DAC output in the baseband circuit. Theory of Operation The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3166 does not use a power detector. A high-speed control loop is incorporated to regulate the collector voltage of the amplifier while the stage are held at a constant bias. The VRAMP signal is multiplied by a factor of 2.3 and the collector voltage for all three stages is regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT
VRAMP 3 dB BW 300 kHz + + H(s) Saturation Detector
RF IN TX ENABLE
RF OUT
By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3166 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
P dBm
( 2 V CC - V SAT ) = 10 log -------------------------------------------3 8 R LOAD 10
2
(Eq. 1)
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are: * * * * * * * * * * Current draw and system efficiency Power variation due to Supply Voltage Power variation due to frequency Power variation due to temperature Input impedance variation Noise power Loop stability Loop bandwidth variations across power levels Burst timing and transient spectrum trade offs Harmonics
Rev A3 061031
2-501
RF3166
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP. The switching transients due to low battery conditions are regulated by the VBATT tracking circuit. The VBATT tracking circuit consists of a feedback loop that detects FET saturation. As the FET approaches saturation, the limiter adjusts the VRAMP voltage in order to ensure minimum switching transients. The VBATT tracking circuit is integrated into the CMOS controller and requires no additional input from the user. Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less. Power variation straight out of the RF3166 is shown in the tables below. The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3166 does not use a directional coupler with a diode detector, these variations do not occur. Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO. The RF3166 presents a very constant load to the VCO. This is because all stages of the RF3166 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier. Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 2),
F2 - 1 F3 - 1 F TOT = F1 + --------------- + ------------------G1 G1 G2
(Eq. 2)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3166 is kept constant the gain in the first stage is always high and the overall noise power is not increased when decreasing output power. Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions. The RF3166 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary.
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RF3166
An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3166 is insensitive to a change in input power and the burst timing is constant and requires no software compensation. Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range or if the slope is simply too steep it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent. Harmonics are natural products of high efficiency power amplifier design. An ideal class "E" saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3166 address this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. Should a problem arise, these terminations should be explored.
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RF3166
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.40 Sq. Typ. B = 0.80 x 0.40 Typ. C = 0.40 x 0.80
0.37 0.93 4.47 5.20 5.60
Dimensions in mm.
A = 0.55 x 0.95 B = 0.55 Sq. Typ. C = 0.95 x 0.55 Typ. D = 1.80 x 4.62 E = 0.60 Sq. Typ.
Pin 1
Pin 1
5.20 4.10 3.30 2.50 1.80 1.40 0.80 0.00
C A A B
B
5.60 5.40 4.90
5.20 TYP 4.10 3.30 2.50 1.60
A B B C B B B D
E E E E E E E E E E E E E E E
C B B B B B B B
5.40 4.62 3.85 3.07 2.76 2.30 1.52 0.75
A A A
0.60 0.20
0.80 0.00
0.00 0.50
4.90 5.40
0.00
1.95
3.40
4.25
Metal Land Pattern
Solder Mask Pattern
Figure 1. PCB Metal Land and Solder Mask Patterns (Top View) PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. Thermal Pad and Via Design Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
2-504
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Rev A3 061031

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